engleski

Silicon nanostrucutres for memory devices

Recently, Si and Ge nanocrystals (ncs) embedded in a silicon dioxide (SiO2) matrix have been widely studied for their luminescence and charge retention properties for integration as opto-electronic and microelectronic devices in complementary metal-oxide-semiconductor (CMOS) technology. As far as memories are concerned, a nc-layer located at a tunneling distance from the Si/SiO2 interface can be used as a floating gate in order to reduce the lateral charge loss limiting conventional flash memories. Samples were prepared by high-vacuum evaporation of a 3 nm thick tunneling SiO2 layer on a n-type silicon substrate with resistivity 10-50  cm, followed by evaporation of a 6 nm thick SiO layer. On top, a 20 nm control oxide was deposited. Upon subsequent thermal annealing in vacuum, Si ncs are formed. The structural properties of the Si ncs are studied by means of grazing incidence small and wide angle x-ray scattering. It is shown that Si nanostructures are formed which crystallinity, size and morphology depends on the annealing temperature. Aluminum electrodes for the front and back sides were evaporated, in order to investigate the charge retention of the samples by means of capacitance-voltage (CV) measurements.

silicon; quantum dots; memory devices

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