engleski

Modeling of surface roughness effects on C-Vcharacteristics of ultra thin MOS capacitors

Permanent scaling of MOS devices pushes the ultrathin gate dielectrics into sub 2-nm regime. Physical mechanisms such as direct tunneling, surface roughness, quantum confinement, and polysilicon depletion must be accounted for determining the gate leakage current and C-V characteristic. Recently it has been demonstrated that the intrinsic reliability limit is fewer than six atomic layers, which is about 1.5 nm. Such thickness of dielectrics is found not only in modern MOS devices but also in solar cells based on quantum structures. In this work we shall explore the impact of tunneling and surface roughness on the gate capacitance of ultra-thin dielectrics. It will be demonstrated that the surface roughness has a dominant impact on C-V characteristics. We shall also show that the direct tunneling dominates over F-N tunneling for the device leakage current. The results will be discussed in the light of application for solar cells using different dielectrics.

MOS ; C-V ; roughness

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